The present invention relates generally to the formation of solder bumps on an integrated circuit device, and more particularly, to the formation of solder bumps having improved height and reliability.
Faster, reliable, and higher-density circuits at lower costs are the goals for integrated circuit (IC) packaging. Conventional wirebond technology, the most common method for electrically connecting aluminum bonding pads on a chip surface to the package inner lead terminals on the lead-frame or substrate has proven to be low cost and reliable. But for the future, packaging goals will be met by increasing the density of chips and reducing the number of internal interconnections. Packages with fewer interconnecting links lower potential failure points, reduce the circuit resistance, and reduce interconnect capacitance, which affects electrical performance. The need to reduce the IC package to fit end-user applications (e.g., smart cards, palmtop computers, camcorders, and so on) is driving the new packaging designs that reduce size and overall profile. This reduction is offset by the need for handling larger amounts of parallel data lines, therefore driving the need to increase package input/output requirements with more leads.
Advanced packaging designs are regularly introduced to solve packaging challenges. One such advanced package design is flip chip or chip scale package (CSP). Flip chip is a packaging method of mounting the active side of a chip (with the surface bonding pads) toward the substrate (i.e., upside down placement of the bumped die relative to the wirebonding approach—thus the reason for the term “flip” chip). It provides the shortest path from the chip devices to the substrate and low cost interconnection for high volume automated production. There is also a reduction in weight and profile since leadframes or plastic packages are often not used. Flip chip technology uses solder bumps—usually formed from tin/lead solder in a 5% Sn and 95% Pb ratio, for example to interconnect the chip bonding pads to the substrate. The solder bumps are generally positioned on the corresponding substrate contact pads and heat, often applied with hot air, and slight pressure then cause the solder bumps to reflow and form solder balls which form the electrical and physical connection between the substrate and the die. There are several methods known to those skilled in the art for producing solder balls on a semiconductor device including evaporation, electroplating, electroless plating, and screen printing.
In practicing the flip chip bonding technology, it has been found that the fatigue life of the solder ball joint is directly proportional to the height of the solder bumps (or solder balls after reflow). An increase in the height of the solder balls reduces the strain observed at the solder ball joints and consequently increases the fatigue life of solder ball joints established between the flip chip and a substrate.
In the evaporation, electroplating, and screen printing techniques for fabricating solder bumps, the final fabrication step is typically a reflow process for the solder bumps wherein a wafer is placed in a furnace, such as a nitrogen containing furnace, for heating the solder bumps to a reflow temperature which is normally the melting temperature of the solder material that forms the balls. The wafers are normally placed in the reflow furnace and typically placed facing up and thus, during the reflow or the melting of the solder bumps, even though the internal force in the bumps tend to draw the balls in a spherical shape, the internal force must balance with the gravity of the solder material and thus, a short or flattened spherical ball of the solder is normally formed. The short or flattened solder balls not only result in a shorter fatigue life, but also result in a small pitch between the balls. It is thus desirable to reduce the pitch of the solder ball arrays in order to accommodate higher level of circuit integration in IC devices that require greater interconnection densities. Further, when a wafer carrier or transport belt is slightly tilted, the flattened solder balls in a molten state may easily touch each other and cause a short circuit in the IC die.
Conventional methods of forming increased solder bump height include increasing the thickness of the photoresist layer so that taller solder material may be plated without the formation of a mushroom-shaped structure. But, this methodology has some challenges due to the limitation the photoresist thickness that can be achieved and the limitation of the exposure procedures. Current photo patterning procedures cannot handle photoresist layers if the photoresist layer is thicker than about 200 μm.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved method of forming solder balls having improved height and reliability that does not have the drawbacks or shortcomings of the conventional methods for forming solder balls. There is a further need for a method of forming solder balls that have improved height such that the pitch between the ball arrays may be increased.